[fpga-miniconf] RISC-V

[Tim 'mithro' Ansell]

We don't use the sifive stuff at all. Currently the only RISC-V processor
that is supported is Clifford's picorv32 ->
https://github.com/cliffordwolf/picorv32. In the future we hope to
add VexRiscv -> https://github.com/SpinalHDL/VexRiscv

I also have not gotten the full RISC-V bare metal toolchain into conda
either, so you will need to compile that yourself. You can see how we do
the conda packages here ->
https://github.com/timvideos/conda-hdmi2usb-packages

FYI -- You can use your Arty with the Freedom stuff without using the LiteX
stuff by just following the instructions here ->
https://www.sifive.com/documentation/freedom-soc/freedom-e300-arty-fpga-dev-kit-getting-started-guide/

Tim 'mithro' Ansell


On 5 February 2018 at 18:56, <Peter.Chubb at data61.csiro.au> wrote:

>
> Has anyone succeded in using the litex-buildenv to install a risc-v
> soft core?  The verilog is available at
> https://github.com/sifive/freedom
>
> So far I've tried setting CPU=riscv64 (the download-env tool fails) or
> CPU=riscv32 (which partly works; conda cannot find an appropriate gcc)
>
> Peter C
>
> --
> Dr Peter Chubb         Tel: +61 2 9490 5852
> http://ts.data61.csiro.au/
> Trustworthy Systems Group                           Data61 (formerly NICTA)
> --
> fpga-miniconf mailing list
> fpga-miniconf at lists.lca2018.linux.org.au
> http://lists.lca2018.linux.org.au/mailman/listinfo/fpga-miniconf
>
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://lists.lca2018.linux.org.au/pipermail/fpga-miniconf/attachments/20180205/a8c56511/attachment-0001.html>