[fpga-miniconf] RISC-V

[Peter.Chubb at data61.csiro.au]

Has anyone succeded in using the litex-buildenv to install a risc-v
soft core?  The verilog is available at
https://github.com/sifive/freedom

So far I've tried setting CPU=riscv64 (the download-env tool fails) or
CPU=riscv32 (which partly works; conda cannot find an appropriate gcc)

Peter C

-- 
Dr Peter Chubb         Tel: +61 2 9490 5852      http://ts.data61.csiro.au/
Trustworthy Systems Group                           Data61 (formerly NICTA)