[fpga-miniconf] Final Reminder of FPGA Miniconf prework and other notes....

Bing Chen Libing.Chen at uts.edu.au
Mon Jan 22 17:43:56 AEDT 2018


Hi Joel/Tim,

Bing's here, I think my kit is faulty or something, when I tried
testing loading gateware on it, I got this error msgs:

--- console msg copy ---

make[1]: Leaving directory '/home/bing/litex-
buildenv/build/arty_net_or1k.linux/software/firmware'

real0m1.135s
user0m1.046s
sys0m0.096s
flterm --port=/dev/ttyUSB1 --
kernel=build/arty_net_or1k.linux//software/firmware/firmware.bin --
speed=115200
[FLTERM] Starting...

LiteX SoC BIOS (or1k)
(c) Copyright 2012-2017 Enjoy-Digital
(c) Copyright 2007-2017 M-Labs Limited
Built Jan 12 2018 04:46:47

BIOS CRC passed (046476c5)
Initializing SDRAM...
Read delays: 1:32-33  0:32-33  completed
Memtest bus failed: 64/256 errors
Memtest data failed: 524288/524288 errors
Memtest addr failed: 8191/8192 errors
Memory initialization failed
BIOS>

----

Then I tried run serialboot and it stuck at "Executing booted program
at 0x40000000"

---- console msg copy ----

BIOS> serialboot
Booting from serial...
Press Q or ESC to abort boot completely.
sL5DdSMmkekro
[FLTERM] Received firmware download request from the device.
[FLTERM] Uploading kernel (74672 bytes)...
[FLTERM] Upload complete (7.7KB/s).
[FLTERM] Booting the device.
[FLTERM] Done.
Executing booted program at 0x40000000

----


Regards
bing

On Sun, 2018-01-21 at 21:19 -0600, joel.stan at gmail.com wrote:
> I will be at the top of the stairs at 3pm with the kits. I'm in a
> blue tshirt. Come say hi and grab your kit.
>
> Cheers,
>
> Joel
>
>
> On 22 Jan. 2018 13:14, "Jason Ball" <jason at ball.net> wrote:
> > For that matter, could I drop in later today to grab the kit so I'm
> > ready for tomorrow's session, latest changes and all.
> >
> > Thanks.
> >
> > On Mon, Jan 22, 2018 at 12:45 PM, Hal Ashburner <hal.ashburner at gmai
> > l.com> wrote:
> > > Hey guys. Where are you set up today?
> > >
> > > On 21 Jan. 2018 7:09 pm, "Tim 'mithro' Ansell" <me at mith.ro>
> > > wrote:
> > > > Hello everyone,
> > > >
> > > > With just over 24 hours until the FPGA Miniconf, this is the
> > > > final reminder that everyone **must** complete the prework at h
> > > > ttp://j.mp/pre-fpga-lca2018
> > > >
> > > > You must complete up to the paragraph which says the following
> > > > in bright red;
> > > > > The instructions from here can only be done after you receive
> > > > > hardware. You can stop here if completing the prework.
> > > >
> > > > If you have not completed the prework you will not be able to
> > > > attend -- that includes observing or anything similar.
> > > >
> > > > If you are stuck, on Monday, 22 Jan 2018, FPGA Miniconf helpers
> > > > will be available to help. They should be available during
> > > > morning tea, lunch and afternoon tea somewhere near the Tomu
> > > > test station. Hopefully they will be able to solve any issues
> > > > you are having.
> > > >
> > > > There will also be an opportunity to pick up the hardware kits
> > > > during lunch at the same location. This will allow you to get a
> > > > head start on setup we need to do at the start of the Miniconf.
> > > >
> > > > It would be a good for everyone to update their litex-buildenv
> > > > sometime Monday evening -- there have been a large number of
> > > > updates since the last email was sent out. This can be done by
> > > > doing the following and then following the prework instructions
> > > > for testing QEmu / Linux.
> > > > > cd litex-buildenv
> > > > > git pull
> > > > > export CPU=or1k PLATFORM=arty TARGET=net
> > > > > ./scripts/download-env.sh
> > > > > source ./scripts/enter-env.sh
> > > >
> > > > Depending on internet speeds, updating should only take 10-15
> > > > minutes.
> > > >
> > > > People are also reminded that the FPGA Miniconf is on Tuesday,
> > > > 23 January 2018 and will be starting at 10:15AM. This is right
> > > > after the Matthew Todd's keynote talk. Please make sure you
> > > > make a beeline from the keynote venue to Large POD Room
> > > > CB11.04.400 when the keynote finishes. Please see the schedule
> > > > email for the full details.
> > > >
> > > > Look forward to seeing everyone on Tuesday!
> > > >
> > > > Tim 'mithro' Ansell
> > > >
> > > > --
> > > > fpga-miniconf mailing list
> > > > fpga-miniconf at lists.lca2018.linux.org.au
> > > > http://lists.lca2018.linux.org.au/mailman/listinfo/fpga-minicon
> > > > f
> > > >
> > >
> > > --
> > > fpga-miniconf mailing list
> > > fpga-miniconf at lists.lca2018.linux.org.au
> > > http://lists.lca2018.linux.org.au/mailman/listinfo/fpga-miniconf
> > >
> >
> >
> >
> > --
> > --
> > Teach your kids Science, or somebody else will :/
> >
> > jason at ball.net
> > vk2vjb at google.com
> > callsign: vk2vjb
> >
> >
> > --
> > fpga-miniconf mailing list
> > fpga-miniconf at lists.lca2018.linux.org.au
> > http://lists.lca2018.linux.org.au/mailman/listinfo/fpga-miniconf
> >
>
>
UTS CRICOS Provider Code: 00099F DISCLAIMER: This email message and any accompanying attachments may contain confidential information. If you are not the intended recipient, do not read, use, disseminate, distribute or copy this message or attachments. If you have received this message in error, please notify the sender immediately and delete this message. Any views expressed in this message are those of the individual sender, except where the sender expressly, and with authority, states them to be the views of the University of Technology Sydney. Before opening any attachments, please check them for viruses and defects. Think. Green. Do. Please consider the environment before printing this email.


More information about the fpga-miniconf mailing list