From hasjim.williams at futaris.org Sun Feb 4 19:35:51 2018 From: hasjim.williams at futaris.org (Hasjim Williams) Date: Sun, 04 Feb 2018 18:35:51 +1000 Subject: [fpga-miniconf] litevideo VGA on arty WIP Message-ID: <1517733351.3054408.1258794560.0C44A4B5@webmail.messagingengine.com> HI everyone, I managed to get Vivado 2016.4 to output VGA with the Pmod-VGA example from: https://reference.digilentinc.com/reference/pmod/pmodvga/start https://github.com/Digilent/Arty-Pmod-VGA https://reference.digilentinc.com/learn/programmable-logic/tutorials/arty-pmod-vga-demo/start I made some changes to litex-buildenv with the help of Florent, and made a pull request on github: https://github.com/timvideos/litex-buildenv/pull/20 This is still WIP and output doesn't work on Pmod-VGA yet in the hdmi2usb firmware. I don't think it's clocking out the pixel clock, hsync and/or vsync correctly yet. Hasjim 'futaris' Williams -------------- next part -------------- An HTML attachment was scrubbed... URL: From f.kermarrec at gmail.com Sun Feb 4 22:16:14 2018 From: f.kermarrec at gmail.com (Florent Kermarrec) Date: Sun, 4 Feb 2018 12:16:14 +0100 Subject: [fpga-miniconf] litevideo VGA on arty WIP In-Reply-To: <1517733351.3054408.1258794560.0C44A4B5@webmail.messagingengine.com> References: <1517733351.3054408.1258794560.0C44A4B5@webmail.messagingengine.com> Message-ID: Hi Hasjim, great, to understand why it's not working yet you can check: - that the video pattern if enabled for the vga output in the firmware. - that you are using a correct video mode (you can start with a low resolution) - if you have a scope, have a look at the clk/vsync/hsync. Florent 2018-02-04 9:35 GMT+01:00 Hasjim Williams : > HI everyone, > > I managed to get Vivado 2016.4 to output VGA with the Pmod-VGA example > from: > > https://reference.digilentinc.com/reference/pmod/pmodvga/start > > https://github.com/Digilent/Arty-Pmod-VGA > https://reference.digilentinc.com/learn/programmable-logic/ > tutorials/arty-pmod-vga-demo/start > > I made some changes to litex-buildenv with the help of Florent, and made a > pull request on github: > > https://github.com/timvideos/litex-buildenv/pull/20 > > This is still WIP and output doesn't work on Pmod-VGA yet in the hdmi2usb > firmware. > > I don't think it's clocking out the pixel clock, hsync and/or vsync > correctly yet. > > Hasjim 'futaris' Williams > > -- > fpga-miniconf mailing list > fpga-miniconf at lists.lca2018.linux.org.au > http://lists.lca2018.linux.org.au/mailman/listinfo/fpga-miniconf > > -------------- next part -------------- An HTML attachment was scrubbed... URL: From jason at ball.net Mon Feb 5 10:32:58 2018 From: jason at ball.net (Jason Ball) Date: Mon, 5 Feb 2018 10:32:58 +1100 Subject: [fpga-miniconf] Were the fpga sessions recorded at all ? Message-ID: I'm working through everything covered to ensure I understand the env and how it all hangs together, but I'm finding a couple of areas where I'm missing details such as enabling access to the fpga logic via a host OS etc. Are there any slides or videos available ? I couldn't see the videos on the youtube listings. J. -- -- Teach your kids Science, or somebody else will :/ jason at ball.net vk2vjb at google.com callsign: vk2vjb -------------- next part -------------- An HTML attachment was scrubbed... URL: From me at mith.ro Mon Feb 5 11:10:59 2018 From: me at mith.ro (Tim 'mithro' Ansell) Date: Sun, 4 Feb 2018 16:10:59 -0800 Subject: [fpga-miniconf] Were the fpga sessions recorded at all ? In-Reply-To: References: Message-ID: There were no recordings of the fpga miniconf sessions as it was mostly interactive tutorial. FYI * There are a bunch of documentation on the litex-buildenv in the wiki here -> https://github.com/timvideos/litex-buildenv/wiki * The migen documentation can be found here -> https://m-labs.hk/migen/manual/ * The slides for my talk on "being an effective FPGA developer " can be found here -> https://docs.google.com/presentation/d/e/2PACX-1vS6nVQOU1sr_6hmRrdazakWBV30DLZ25tzuLGHCxYg62Jp1Riiy7NDbuk9WrVdaezQvi5QKP96vDV28/pub?start=false&loop=false&delayms=3000 Feel free to ask questions on the list and we will try and answer them! Hope that helps! Tim 'mithro' Ansell On 4 February 2018 at 15:32, Jason Ball wrote: > > I'm working through everything covered to ensure I understand the env and > how it all hangs together, but I'm finding a couple of areas where I'm > missing details such as enabling access to the fpga logic via a host OS etc. > > Are there any slides or videos available ? I couldn't see the videos on > the youtube listings. > > J. > > -------------- next part -------------- An HTML attachment was scrubbed... URL: From hasjim.williams at futaris.org Mon Feb 5 11:24:05 2018 From: hasjim.williams at futaris.org (Hasjim Williams) Date: Mon, 05 Feb 2018 10:24:05 +1000 Subject: [fpga-miniconf] litevideo VGA on arty WIP In-Reply-To: References: <1517733351.3054408.1258794560.0C44A4B5@webmail.messagingengine.com> Message-ID: <1517790245.2910016.1259318368.7A30D146@webmail.messagingengine.com> Hi Florent, As I suspected, something is weird with the clocking, and the G0 output doesn't appear to changing... I posted some oscilloscope screenshots on #timvideos. I'm not sure that I've done the firmware code correctly. I've basically taken the HDMI_OUT0 stuff and search/replaced with VGA_OUT0. I haven't really looked into how the MMCM works, or the PLL on the MimasV2, so I'm sure I've messed up something. Is there any documentation on the simulator / verilator and how to run litevideo in it ? Hasjim On Sun, Feb 4, 2018, at 9:16 PM, Florent Kermarrec wrote: > Hi Hasjim, > > great, to understand why it's not working yet you can check: > - that the video pattern if enabled for the vga output in the > firmware.> - that you are using a correct video mode (you can start with a low > resolution)> - if you have a scope, have a look at the clk/vsync/hsync. > > Florent > > 2018-02-04 9:35 GMT+01:00 Hasjim Williams > :>> __ >> HI everyone, >> >> I managed to get Vivado 2016.4 to output VGA with the Pmod-VGA >> example from:>> >> https://reference.digilentinc.com/reference/pmod/pmodvga/start >> >> https://github.com/Digilent/Arty-Pmod-VGA >> https://reference.digilentinc.com/learn/programmable-logic/tutorials/arty-pmod-vga-demo/start>> >> I made some changes to litex-buildenv with the help of Florent, and >> made a pull request on github:>> >> https://github.com/timvideos/litex-buildenv/pull/20 >> >> This is still WIP and output doesn't work on Pmod-VGA yet in the >> hdmi2usb firmware.>> >> I don't think it's clocking out the pixel clock, hsync and/or vsync >> correctly yet.>> >> Hasjim 'futaris' Williams >> >> -- >> fpga-miniconf mailing list >> fpga-miniconf at lists.lca2018.linux.org.au >> http://lists.lca2018.linux.org.au/mailman/listinfo/fpga-miniconf >> -------------- next part -------------- An HTML attachment was scrubbed... URL: From f.kermarrec at gmail.com Mon Feb 5 19:36:23 2018 From: f.kermarrec at gmail.com (Florent Kermarrec) Date: Mon, 5 Feb 2018 09:36:23 +0100 Subject: [fpga-miniconf] litevideo VGA on arty WIP In-Reply-To: <1517790245.2910016.1259318368.7A30D146@webmail.messagingengine.com> References: <1517733351.3054408.1258794560.0C44A4B5@webmail.messagingengine.com> <1517790245.2910016.1259318368.7A30D146@webmail.messagingengine.com> Message-ID: Hi Hasjim, it's strange you don't have at least the clock on the output. First thing to check is that your pix clock is working. Your changes in the firmware seem fine, but you can try to connect one led to a counter clocked by pix_clk to make sure your are configuring the mmcm correctly. Florent 2018-02-05 1:24 GMT+01:00 Hasjim Williams : > Hi Florent, > > As I suspected, something is weird with the clocking, and the G0 output > doesn't appear to changing... > > I posted some oscilloscope screenshots on #timvideos. > > I'm not sure that I've done the firmware code correctly. I've basically > taken the HDMI_OUT0 stuff and search/replaced with VGA_OUT0. > > I haven't really looked into how the MMCM works, or the PLL on the > MimasV2, so I'm sure I've messed up something. > > Is there any documentation on the simulator / verilator and how to run > litevideo in it ? > > Hasjim > > On Sun, Feb 4, 2018, at 9:16 PM, Florent Kermarrec wrote: > > Hi Hasjim, > > great, to understand why it's not working yet you can check: > - that the video pattern if enabled for the vga output in the firmware. > - that you are using a correct video mode (you can start with a low > resolution) > - if you have a scope, have a look at the clk/vsync/hsync. > > Florent > > 2018-02-04 9:35 GMT+01:00 Hasjim Williams : > > > HI everyone, > > I managed to get Vivado 2016.4 to output VGA with the Pmod-VGA example > from: > > https://reference.digilentinc.com/reference/pmod/pmodvga/start > > https://github.com/Digilent/Arty-Pmod-VGA > https://reference.digilentinc.com/learn/programmable-logic/t > utorials/arty-pmod-vga-demo/start > > I made some changes to litex-buildenv with the help of Florent, and made a > pull request on github: > > https://github.com/timvideos/litex-buildenv/pull/20 > > This is still WIP and output doesn't work on Pmod-VGA yet in the hdmi2usb > firmware. > > I don't think it's clocking out the pixel clock, hsync and/or vsync > correctly yet. > > Hasjim 'futaris' Williams > > -- > fpga-miniconf mailing list > fpga-miniconf at lists.lca2018.linux.org.au > http://lists.lca2018.linux.org.au/mailman/listinfo/fpga-miniconf > > > -------------- next part -------------- An HTML attachment was scrubbed... URL: From hasjim.williams at futaris.org Mon Feb 5 20:27:25 2018 From: hasjim.williams at futaris.org (Hasjim Williams) Date: Mon, 05 Feb 2018 19:27:25 +1000 Subject: [fpga-miniconf] litevideo VGA on arty WIP In-Reply-To: References: <1517733351.3054408.1258794560.0C44A4B5@webmail.messagingengine.com> <1517790245.2910016.1259318368.7A30D146@webmail.messagingengine.com> Message-ID: <1517822845.1055718.1259669768.27AD1F56@webmail.messagingengine.com> Hi Florent, So, I just need to do something like: https://github.com/futaris/litex-buildenv/blob/master/targets/nexys_video/video.py#L128 Is this the best documentation on how the mmcm & clocking works on Artix-7?https://www.xilinx.com/support/documentation/user_guides/ug472_7Series_Clocking.pdf HDMI/DVI clocks 10 times faster for the pixels, compared to the main clock, right? VGA clocks once per pixel, so I will probably have to modify that. Can I hard code the pixel clock in the gateware, rather than use the pix clock? Hasjim On Mon, Feb 5, 2018, at 6:36 PM, Florent Kermarrec wrote: > Hi Hasjim, > > it's strange you don't have at least the clock on the output. First > thing to check is that your pix clock is working.> Your changes in the firmware seem fine, but you can try to connect one > led to a counter clocked by pix_clk to make sure your are configuring > the mmcm correctly.> > Florent > > 2018-02-05 1:24 GMT+01:00 Hasjim Williams > :>> __ >> Hi Florent, >> >> As I suspected, something is weird with the clocking, and the G0 >> output doesn't appear to changing...>> >> I posted some oscilloscope screenshots on #timvideos. >> >> I'm not sure that I've done the firmware code correctly. I've >> basically taken the HDMI_OUT0 stuff and search/replaced with >> VGA_OUT0.>> >> I haven't really looked into how the MMCM works, or the PLL on the >> MimasV2, so I'm sure I've messed up something.>> >> Is there any documentation on the simulator / verilator and how to >> run litevideo in it ?>> >> >> Hasjim >> >> >> On Sun, Feb 4, 2018, at 9:16 PM, Florent Kermarrec wrote: >>> Hi Hasjim, >>> >>> great, to understand why it's not working yet you can check: >>> - that the video pattern if enabled for the vga output in the >>> firmware.>>> - that you are using a correct video mode (you can start with a low >>> resolution)>>> - if you have a scope, have a look at the clk/vsync/hsync. >>> >>> Florent >>> >>> 2018-02-04 9:35 GMT+01:00 Hasjim Williams >>> :>>>> __ >>>> HI everyone, >>>> >>>> I managed to get Vivado 2016.4 to output VGA with the Pmod-VGA >>>> example from:>>>> >>>> https://reference.digilentinc.com/reference/pmod/pmodvga/start>>>> >>>> https://github.com/Digilent/Arty-Pmod-VGA >>>> https://reference.digilentinc.com/learn/programmable-logic/tutorials/arty-pmod-vga-demo/start>>>> >>>> I made some changes to litex-buildenv with the help of Florent, and >>>> made a pull request on github:>>>> >>>> https://github.com/timvideos/litex-buildenv/pull/20 >>>> >>>> This is still WIP and output doesn't work on Pmod-VGA yet in the >>>> hdmi2usb firmware.>>>> >>>> I don't think it's clocking out the pixel clock, hsync and/or vsync >>>> correctly yet.>>>> >>>> Hasjim 'futaris' Williams >>>> >>>> -- >>>> fpga-miniconf mailing list >>>> fpga-miniconf at lists.lca2018.linux.org.au >>>> http://lists.lca2018.linux.org.au/mailman/listinfo/fpga-miniconf >>>> >> -------------- next part -------------- An HTML attachment was scrubbed... URL: From f.kermarrec at gmail.com Mon Feb 5 21:12:23 2018 From: f.kermarrec at gmail.com (Florent Kermarrec) Date: Mon, 5 Feb 2018 11:12:23 +0100 Subject: [fpga-miniconf] litevideo VGA on arty WIP In-Reply-To: <1517822845.1055718.1259669768.27AD1F56@webmail.messagingengine.com> References: <1517733351.3054408.1258794560.0C44A4B5@webmail.messagingengine.com> <1517790245.2910016.1259318368.7A30D146@webmail.messagingengine.com> <1517822845.1055718.1259669768.27AD1F56@webmail.messagingengine.com> Message-ID: > > So, I just need to do something like: > https://github.com/futaris/litex-buildenv/blob/master/ > targets/nexys_video/video.py#L128 > Yes you can do that. > > Is this the best documentation on how the mmcm & clocking works on > Artix-7? > https://www.xilinx.com/support/documentation/user_ > guides/ug472_7Series_Clocking.pdf > That's the right document. > > HDMI/DVI clocks 10 times faster for the pixels, compared to the main > clock, right? > > VGA clocks once per pixel, so I will probably have to modify that. > In both case we are outputing the pixel clock. Just that for HDMI/DVI data are serialized and use 10b/8b so yes 10 times faster than clock. > Can I hard code the pixel clock in the gateware, rather than use the pix > clock? > Yes you can, just set the default parameters of this MMCME2_ADV to the values you want: https://github.com/enjoy-digital/litevideo/blob/master/litevideo/output/hdmi/s7.py#L100 Florent > On Mon, Feb 5, 2018, at 6:36 PM, Florent Kermarrec wrote: > > Hi Hasjim, > > it's strange you don't have at least the clock on the output. First thing > to check is that your pix clock is working. > Your changes in the firmware seem fine, but you can try to connect one led > to a counter clocked by pix_clk to make sure your are configuring the mmcm > correctly. > > Florent > > 2018-02-05 1:24 GMT+01:00 Hasjim Williams : > > > Hi Florent, > > As I suspected, something is weird with the clocking, and the G0 output > doesn't appear to changing... > > I posted some oscilloscope screenshots on #timvideos. > > I'm not sure that I've done the firmware code correctly. I've basically > taken the HDMI_OUT0 stuff and search/replaced with VGA_OUT0. > > I haven't really looked into how the MMCM works, or the PLL on the > MimasV2, so I'm sure I've messed up something. > > Is there any documentation on the simulator / verilator and how to run > litevideo in it ? > > > Hasjim > > > On Sun, Feb 4, 2018, at 9:16 PM, Florent Kermarrec wrote: > > Hi Hasjim, > > great, to understand why it's not working yet you can check: > - that the video pattern if enabled for the vga output in the firmware. > - that you are using a correct video mode (you can start with a low > resolution) > - if you have a scope, have a look at the clk/vsync/hsync. > > Florent > > 2018-02-04 9:35 GMT+01:00 Hasjim Williams : > > > HI everyone, > > I managed to get Vivado 2016.4 to output VGA with the Pmod-VGA example > from: > > https://reference.digilentinc.com/reference/pmod/pmodvga/start > > https://github.com/Digilent/Arty-Pmod-VGA > https://reference.digilentinc.com/learn/programmable-logic/t > utorials/arty-pmod-vga-demo/start > > I made some changes to litex-buildenv with the help of Florent, and made a > pull request on github: > > https://github.com/timvideos/litex-buildenv/pull/20 > > This is still WIP and output doesn't work on Pmod-VGA yet in the hdmi2usb > firmware. > > I don't think it's clocking out the pixel clock, hsync and/or vsync > correctly yet. > > Hasjim 'futaris' Williams > > -- > fpga-miniconf mailing list > fpga-miniconf at lists.lca2018.linux.org.au > http://lists.lca2018.linux.org.au/mailman/listinfo/fpga-miniconf > > > > -------------- next part -------------- An HTML attachment was scrubbed... URL: From Peter.Chubb at data61.csiro.au Tue Feb 6 13:56:12 2018 From: Peter.Chubb at data61.csiro.au (Peter.Chubb at data61.csiro.au) Date: Tue, 6 Feb 2018 02:56:12 +0000 Subject: [fpga-miniconf] RISC-V Message-ID: <84inbaq10z.wl-Peter.Chubb@data61.csiro.au> Has anyone succeded in using the litex-buildenv to install a risc-v soft core? The verilog is available at https://github.com/sifive/freedom So far I've tried setting CPU=riscv64 (the download-env tool fails) or CPU=riscv32 (which partly works; conda cannot find an appropriate gcc) Peter C -- Dr Peter Chubb Tel: +61 2 9490 5852 http://ts.data61.csiro.au/ Trustworthy Systems Group Data61 (formerly NICTA) From me at mith.ro Tue Feb 6 14:13:04 2018 From: me at mith.ro (Tim 'mithro' Ansell) Date: Mon, 5 Feb 2018 19:13:04 -0800 Subject: [fpga-miniconf] RISC-V In-Reply-To: <84inbaq10z.wl-Peter.Chubb@data61.csiro.au> References: <84inbaq10z.wl-Peter.Chubb@data61.csiro.au> Message-ID: We don't use the sifive stuff at all. Currently the only RISC-V processor that is supported is Clifford's picorv32 -> https://github.com/cliffordwolf/picorv32. In the future we hope to add VexRiscv -> https://github.com/SpinalHDL/VexRiscv I also have not gotten the full RISC-V bare metal toolchain into conda either, so you will need to compile that yourself. You can see how we do the conda packages here -> https://github.com/timvideos/conda-hdmi2usb-packages FYI -- You can use your Arty with the Freedom stuff without using the LiteX stuff by just following the instructions here -> https://www.sifive.com/documentation/freedom-soc/freedom-e300-arty-fpga-dev-kit-getting-started-guide/ Tim 'mithro' Ansell On 5 February 2018 at 18:56, wrote: > > Has anyone succeded in using the litex-buildenv to install a risc-v > soft core? The verilog is available at > https://github.com/sifive/freedom > > So far I've tried setting CPU=riscv64 (the download-env tool fails) or > CPU=riscv32 (which partly works; conda cannot find an appropriate gcc) > > Peter C > > -- > Dr Peter Chubb Tel: +61 2 9490 5852 > http://ts.data61.csiro.au/ > Trustworthy Systems Group Data61 (formerly NICTA) > -- > fpga-miniconf mailing list > fpga-miniconf at lists.lca2018.linux.org.au > http://lists.lca2018.linux.org.au/mailman/listinfo/fpga-miniconf > -------------- next part -------------- An HTML attachment was scrubbed... URL: From me at mith.ro Sat Feb 10 02:45:26 2018 From: me at mith.ro (Tim 'mithro' Ansell) Date: Fri, 9 Feb 2018 07:45:26 -0800 Subject: [fpga-miniconf] Anyone have photos + thoughts on FPGA Miniconf? In-Reply-To: References:

Message-ID: Hi everyone! If you have any photos or thoughts (hopefully positive?) on the FPGA Miniconf, can you send them my way? Digilent are going to do a blog post about the event and are looking for images and quotes. As Digilent's blog has a large reach to both FPGA professionals and people in the academic space (including a huge number of students who have to use Digilent's hardware as part of their course work) it would be good to advertise LiteX and the litex-buildenv. With TimVideos applying to Google Summer of Code and hoping to get students to work on LiteX and/or litex-buildenv it would be awesome to put our best foot forward with this advertisement opportunity. Hope you are all doing cool things with your FPGA hardware, thank you! Tim 'mithro' Ansell -------------- next part -------------- An HTML attachment was scrubbed... URL: From alastair at d-silva.org Sat Feb 10 10:29:31 2018 From: alastair at d-silva.org (Alastair D'Silva) Date: Sat, 10 Feb 2018 10:29:31 +1100 Subject: [fpga-miniconf] Anyone have photos + thoughts on FPGA Miniconf? In-Reply-To: References:

Message-ID: <2873701d3a1fd$d7291cf0$857b56d0$@d-silva.org> Hi Tim, There was a fair amount of content during the day, but not much in the way of take home information. I worry that by the time I get around to playing more with the kit, I?ll have forgotten it. Can we have workshop writeups made available so we can follow along at home? -- Alastair D'Silva mob: 0423 762 819 skype: alastair_dsilva msn: alastair at d-silva.org blog: http://alastair.d-silva.org Twitter: @EvilDeece From: fpga-miniconf [mailto:fpga-miniconf-bounces at lists.lca2018.linux.org.au] On Behalf Of Tim 'mithro' Ansell Sent: Saturday, 10 February 2018 2:45 AM To: fpga-miniconf Subject: [fpga-miniconf] Anyone have photos + thoughts on FPGA Miniconf? Hi everyone! If you have any photos or thoughts (hopefully positive?) on the FPGA Miniconf, can you send them my way? Digilent are going to do a blog post about the event and are looking for images and quotes. As Digilent's blog has a large reach to both FPGA professionals and people in the academic space (including a huge number of students who have to use Digilent's hardware as part of their course work) it would be good to advertise LiteX and the litex-buildenv. With TimVideos applying to Google Summer of Code and hoping to get students to work on LiteX and/or litex-buildenv it would be awesome to put our best foot forward with this advertisement opportunity. Hope you are all doing cool things with your FPGA hardware, thank you! Tim 'mithro' Ansell Virus-free. www.avg.com -------------- next part -------------- An HTML attachment was scrubbed... URL: From bunnie at bunniestudios.com Sat Feb 10 12:43:27 2018 From: bunnie at bunniestudios.com (bunnie) Date: Sat, 10 Feb 2018 09:43:27 +0800 Subject: [fpga-miniconf] Anyone have photos + thoughts on FPGA Miniconf? In-Reply-To: <2873701d3a1fd$d7291cf0$857b56d0$@d-silva.org> References:

<2873701d3a1fd$d7291cf0$857b56d0$@d-silva.org> Message-ID: I second that. In particular I was looking for the gist/github repos that the code covered that day was located in, but couldn't find it in my notes or anywhere in the email threads? thanks, -b. On 02/10/2018 07:29 AM, Alastair D'Silva wrote: > Hi Tim, > > ? > > There was a fair amount of content during the day, but not much in the > way of take home information. I worry that by the time I get around to > playing more with the kit, I?ll have forgotten it. Can we have workshop > writeups made available so we can follow along at home? > > ? > > -- > > Alastair D'Silva?????????? mob: 0423 762 819 > > skype: alastair_dsilva???? msn: alastair at d-silva.org > > blog: http://alastair.d-silva.org??? Twitter: @EvilDeece > > ? > > ? > > ? > > *From:*fpga-miniconf > [mailto:fpga-miniconf-bounces at lists.lca2018.linux.org.au] *On Behalf Of > *Tim 'mithro' Ansell > *Sent:* Saturday, 10 February 2018 2:45 AM > *To:* fpga-miniconf > *Subject:* [fpga-miniconf] Anyone have photos + thoughts on FPGA Miniconf? > > ? > > Hi everyone! > > ? > > If you have any photos or thoughts (hopefully positive?) on the FPGA > Miniconf, can you send them my way? > > ? > > Digilent are going to do a blog post about the event and are looking for > images and quotes.? > > ? > > As Digilent's blog has a large reach to both FPGA professionals and > people in the academic space (including a huge number of students who > have to use Digilent's hardware as part of their course work) it would > be good to advertise LiteX and the litex-buildenv.? > > ? > > With TimVideos applying to Google Summer of Code and hoping to get > students to work on LiteX and/or litex-buildenv it would be awesome to > put our best foot forward with this advertisement opportunity. > > ? > > Hope you are all doing cool things with your FPGA hardware, thank you! > > ? > > Tim 'mithro' Ansell > > ? > > > > > > Virus-free. www.avg.com > > > > ? > > > -- ^`'~*-,._.^`'~*-,._.^`'~*-,._.^`'~*-,._.^`'~*-,._.^`'~*-,._.^`'~*-,._.^`' From hasjim.williams at futaris.org Sat Feb 10 12:51:24 2018 From: hasjim.williams at futaris.org (Hasjim Williams) Date: Sat, 10 Feb 2018 11:51:24 +1000 Subject: [fpga-miniconf] Anyone have photos + thoughts on FPGA Miniconf? In-Reply-To: References:

<2873701d3a1fd$d7291cf0$857b56d0$@d-silva.org> Message-ID: <1518227484.2573625.1265937408.6F6D6407@webmail.messagingengine.com> I believe this is the repo you're looking for: https://github.com/jimmo/litex-buildenv/commits/lca-leds Hasjim On Sat, Feb 10, 2018, at 11:43 AM, bunnie wrote: > I second that. In particular I was looking for the gist/github repos > that the code covered that day was located in, but couldn't find it in> my notes or anywhere in the email threads? > > thanks, > > -b. > > On 02/10/2018 07:29 AM, Alastair D'Silva wrote: >> Hi Tim, >> >> >> >> There was a fair amount of content during the day, but not >> much in the>> way of take home information. I worry that by the time I get >> around to>> playing more with the kit, I?ll have forgotten it. Can we have >> workshop>> writeups made available so we can follow along at home? >> >> >> >> -- >> >> Alastair D'Silva mob: 0423 762 819 >> >> skype: alastair_dsilva msn: alastair at d-silva.org >> >> blog: http://alastair.d-silva.org Twitter: @EvilDeece >> >> >> >> >> >> >> >> *From:*fpga-miniconf >> [mailto:fpga-miniconf-bounces at lists.lca2018.linux.org.au] *On >> Behalf Of>> *Tim 'mithro' Ansell >> **Sent:** Saturday, 10 February 2018 2:45 AM >> **To:** fpga-miniconf >> **Subject:** [fpga-miniconf] Anyone have photos + thoughts on FPGA >> Miniconf?>> >> >> >> Hi everyone! >> >> >> >> If you have any photos or thoughts (hopefully positive?) on the FPGA>> Miniconf, can you send them my way? >> >> >> >> Digilent are going to do a blog post about the event and are >> looking for>> images and quotes. >> >> >> >> As Digilent's blog has a large reach to both FPGA professionals and >> people in the academic space (including a huge number of students who>> have to use Digilent's hardware as part of their course work) >> it would>> be good to advertise LiteX and the litex-buildenv. >> >> >> >> With TimVideos applying to Google Summer of Code and hoping to get >> students to work on LiteX and/or litex-buildenv it would be >> awesome to>> put our best foot forward with this advertisement opportunity. >> >> >> >> Hope you are all doing cool things with your FPGA hardware, >> thank you!>> >> >> >> Tim 'mithro' Ansell >> >> >> >> >> >> >> >> Virus-free. www.avg.com >> >> >> >> >> >> >> > > -- > ^`'~*-,._.^`'~*-,._.^`'~*-,._.^`'~*-,._.^`'~*-,._.^`'~*- > ,._.^`'~*-,._.^`'> -- > fpga-miniconf mailing list > fpga-miniconf at lists.lca2018.linux.org.au > http://lists.lca2018.linux.org.au/mailman/listinfo/fpga-miniconf -------------- next part -------------- An HTML attachment was scrubbed... URL: